LP
Career profile
Luigi Pantisano
Senior Staff Reliability Engineer (Ph.D.) | SoC & Advanced Packaging (2.5D/3D) | System-Level Reliability (Data Center & Auto) | NPI Qualification Strategy
Portland, Oregon, United States
Career path.
- Intellibank
TD R&D Reliability engineer
May 2021 - Present - GlobalFoundries
CMOS Device and Reliability Engineer, Globalfoundries
Apr 2015 - Sep 2016 - GlobalFoundries
Quality and Reliability Engineering Manager
Jul 2012 - Sep 2016 - GlobalFoundries
Manager / Senior Staff, TD Reliability CMOS, finfet RF and Automotive products
Jul 2012 - May 2021 - GIST, Gwang-Ju (South Korea)
Associate Professor (part-time)
Jun 2009 - Aug 2011 - imec
Senior Scientist
Apr 2001 - Jun 2012 - Bell Laboratories
Student Researcher
Mar 2000 - Mar 2001